/** @file

Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
  list of conditions and the following disclaimer in the documentation and/or
  other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
  be used to endorse or promote products derived from this software without
  specific prior written permission.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  THE POSSIBILITY OF SUCH DAMAGE.

  This file is automatically generated. Please do NOT modify !!!

**/

#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__

#include "FspUpd.h"


/** Fsp S Configuration
**/
struct FSP_S_CONFIG {

/** Offset 0x0020 - ActiveProcessorCores
  Number of active cores.
**/
  uint8_t                       ActiveProcessorCores;

/** Offset 0x0021 - Disable Core1
  Disable/Enable Core1.
  $EN_DIS
**/
  uint8_t                       DisableCore1;

/** Offset 0x0022 - Disable Core2
  Disable/Enable Core2.
  $EN_DIS
**/
  uint8_t                       DisableCore2;

/** Offset 0x0023 - Disable Core3
  Disable/Enable Core3.
  $EN_DIS
**/
  uint8_t                       DisableCore3;

/** Offset 0x0024 - VMX Enable
  Enable or Disable VMX.
  $EN_DIS
**/
  uint8_t                       VmxEnable;

/** Offset 0x0025 - Memory region allocation for Processor Trace
  Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); <b>0xFF: Disable.
**/
  uint8_t                       ProcTraceMemSize;

/** Offset 0x0026 - Enable Processor Trace
  Enable or Disable Processor Trace feature.
  $EN_DIS
**/
  uint8_t                       ProcTraceEnable;

/** Offset 0x0027 - Eist
  Enable or Disable Intel SpeedStep Technology.
  $EN_DIS
**/
  uint8_t                       Eist;

/** Offset 0x0028 - Boot PState
  Boot PState with HFM or LFM. 0: HFM; 1: LFM.
**/
  uint8_t                       BootPState;

/** Offset 0x0029 - CPU power states (C-states)
  Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable.
  $EN_DIS
**/
  uint8_t                       EnableCx;

/** Offset 0x002A - Enhanced C-states
  Enable or Disable Enhanced C-states. 0: Disable; 1: Enable.
  $EN_DIS
**/
  uint8_t                       C1e;

/** Offset 0x002B - Bi-Directional PROCHOT#
  Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable.
  $EN_DIS
**/
  uint8_t                       BiProcHot;

/** Offset 0x002C - Max Pkg Cstate
  Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto.
**/
  uint8_t                       PkgCStateLimit;

/** Offset 0x002D
**/
  uint8_t                       UnusedUpdSpace0;

/** Offset 0x002E - C-State auto-demotion
  C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3.
**/
  uint8_t                       CStateAutoDemotion;

/** Offset 0x002F - C-State un-demotion
  C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion.
**/
  uint8_t                       CStateUnDemotion;

/** Offset 0x0030 - Max Core C-State
  Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx.
**/
  uint8_t                       MaxCoreCState;

/** Offset 0x0031 - Package C-State Demotion
  Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable.
  $EN_DIS
**/
  uint8_t                       PkgCStateDemotion;

/** Offset 0x0032 - Package C-State Un-demotion
  Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable.
  $EN_DIS
**/
  uint8_t                       PkgCStateUnDemotion;

/** Offset 0x0033 - Turbo Mode
  Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable.
  $EN_DIS
**/
  uint8_t                       TurboMode;

/** Offset 0x0034
**/
  uint8_t                       UnusedUpdSpace1[12];

/** Offset 0x0040 - HD-Audio I/O Buffer Ownership
  Set HD-Audio I/O Buffer Ownership.
  0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
**/
  uint8_t                       HdAudioIoBufferOwnership;

/** Offset 0x0041
**/
  uint8_t                       UnusedUpdSpace2[5];

/** Offset 0x0046 - Enable SD controller
  Enable/disable SD Card controller.
  $EN_DIS
**/
  uint8_t                       SdcardEnabled;

/** Offset 0x0047 - Enable SDIO controller
  Enable/disable SDIO controller.
  $EN_DIS
**/
  uint8_t                       SdioEnabled;

/** Offset 0x0048 - Enable eMMC controller
  Enable/disable eMMC controller.
  $EN_DIS
**/
  uint8_t                       eMMCEnabled;

/** Offset 0x0049 - Enable SATA
  Enable/disable SATA controller.
  $EN_DIS
**/
  uint8_t                       EnableSata;

/** Offset 0x004A - SATA Mode
  Select SATA controller working mode.
  0:AHCI, 1:RAID
**/
  uint8_t                       SataMode;

/** Offset 0x004B - Aggressive SATA LPM Support
  Enable SOC to aggressively enter link power state for SATA.
  $EN_DIS
**/
  uint8_t                       SataSalpSupport;

/** Offset 0x004C - Enable SATA ports
  Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
**/
  uint8_t                       SataPortsEnable[2];

/** Offset 0x004E - Enable SATA DEVSLP Feature
  Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on.
**/
  uint8_t                       SataPortsDevSlp[2];

/** Offset 0x0050 - Enable PCIE RP
  Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
**/
  uint8_t                       PcieRootPortEn[6];

/** Offset 0x0056 - Configure CLKREQ Number
  Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
**/
  uint8_t                       PcieRpClkReqNumber[6];

/** Offset 0x005C
**/
  uint8_t                       UnusedUpdSpace3[16];

/** Offset 0x006C - Enable USB2 ports
  Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
**/
  uint8_t                       PortUsb20Enable[8];

/** Offset 0x0074 - Enable USB3 ports
  Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
**/
  uint8_t                       PortUsb30Enable[6];

/** Offset 0x007A - Enable XHCI SSIC ports
  Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1.
**/
  uint8_t                       SsicPortEnable[2];

/** Offset 0x007C - Enable SMBus
  Enable/disable SMBus controller.
  $EN_DIS
**/
  uint8_t                       SmbusEnable;

/** Offset 0x007D - SC HDA Verb Table Entry Number
  Number of Entries in Verb Table.
**/
  uint8_t                       HdaVerbTableEntryNum;

/** Offset 0x007E - SC HDA Verb Table Pointer
  Pointer to Array of pointers to Verb Table.
**/
  uint32_t                      HdaVerbTablePtr;

/** Offset 0x0082
**/
  uint8_t                       UnusedUpdSpace4[14];

/** Offset 0x0090 - Enable/Disable P2SB device hidden.
  Enable/Disable P2SB device hidden.
  $EN_DIS
**/
  uint8_t                       HideP2sb;

/** Offset 0x0091 - Ufs Enable/Disable
  Enable/Disable Ufs.
  $EN_DIS
**/
  uint8_t                       UfsEnabled;

/** Offset 0x0092 - IPU Enable/Disable
  Enable/Disable IPU Device.
  $EN_DIS
**/
  uint8_t                       IpuEn;

/** Offset 0x0093 - IMGU ACPI mode selection
  0=Auto, 1(Default)=IGFX Child device, 2=ACPI device
  0:Disable, 1:IGFX Child device, 2:ACPI device
**/
  uint8_t                       IpuAcpiMode;

/** Offset 0x0094 - ResetSelect
  ResetSelect. 0x6:warm reset; 0xE:cold reset
**/
  uint8_t                       ResetSelect;

/** Offset 0x0095 - CRIDSettings
  PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3
**/
  uint8_t                       CRIDSettings;

/** Offset 0x0096 - Enable HPET
  Enable/disable HPET.
  $EN_DIS
**/
  uint8_t                       Hpet;

/** Offset 0x0097 - Enable PCIE Clock Gating
  Enable/disable PCIE Clock Gating.0:Enable;1:Disable
  $EN_DIS
**/
  uint8_t                       PcieClockGatingDisabled;

/** Offset 0x0098 - Enable PCIE Root Port 8xh Decode
  Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       PcieRootPort8xhDecode;

/** Offset 0x0099 - PCIE 8xh Decode Port Index
  PCIE 8xh Decode Port Index.
**/
  uint8_t                       Pcie8xhDecodePortIndex;

/** Offset 0x009A - Enable PCIE Root Port Peer Memory Write
  Enable/disable PCIE root port peer memory write.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       PcieRootPortPeerMemoryWriteEnable;

/** Offset 0x009B - Enable SC Gaussian Mixture Models
  Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       Gmm;

/** Offset 0x009C - GttMmAdr
  GttMmAdr structure for initialization.
**/
  uint32_t                      GttMmAdr;

/** Offset 0x00A0
**/
  uint8_t                       UnusedUpdSpace5[96];

/** Offset 0x0100 - Enable S0ix
  Enable/disable S0ix.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       S0ix;

/** Offset 0x0101 - GmAdr
  GmAdr structure for initialization.
**/
  uint32_t                      GmAdr;

/** Offset 0x0105 - Enable ForceWake
  Enable/disable ForceWake Models.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       ForceWake;

/** Offset 0x0106 - Enable PavpLock
  Enable/disable PavpLock.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       PavpLock;

/** Offset 0x0107 - Enable GraphicsFreqModify
  Enable/disable GraphicsFreqModify.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       GraphicsFreqModify;

/** Offset 0x0108 - Enable GraphicsFreqReq
  Enable/disable GraphicsFreqReq.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       GraphicsFreqReq;

/** Offset 0x0109 - Enable GraphicsVideoFreq
  Enable/disable GraphicsVideoFreq.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       GraphicsVideoFreq;

/** Offset 0x010A - Enable PmLock
  Enable/disable PmLock.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       PmLock;

/** Offset 0x010B
**/
  uint8_t                       UnusedUpdSpace6[5];

/** Offset 0x0110 - Enable DopClockGating
  Enable/disable DopClockGating.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       DopClockGating;

/** Offset 0x0111 - Enable UnsolicitedAttackOverride
  Enable/disable UnsolicitedAttackOverride.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       UnsolicitedAttackOverride;

/** Offset 0x0112 - Enable WOPCMSupport
  Enable/disable WOPCMSupport.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       WOPCMSupport;

/** Offset 0x0113 - Enable WOPCMSize
  Enable/disable WOPCMSize.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       WOPCMSize;

/** Offset 0x0114 - Enable PowerGating
  Enable/disable PowerGating.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       PowerGating;

/** Offset 0x0115 - Enable UnitLevelClockGating
  Enable/disable UnitLevelClockGating.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       UnitLevelClockGating;

/** Offset 0x0116 - Enable FastBoot
  Enable/disable FastBoot.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       FastBoot;

/** Offset 0x0117 - Enable DynSR
  Enable/disable DynSR.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       DynSR;

/** Offset 0x0118 - Enable SaIpuEnable
  Enable/disable SaIpuEnable.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       SaIpuEnable;

/** Offset 0x0119 - Enable VtdEnable
  Enable/disable VtdEnable.0:Disable;1:Enable
  $EN_DIS
**/
  uint8_t                       VtdEnable;

/** Offset 0x011A - BMP Logo Data Size
  BMP logo data buffer size.
**/
  uint32_t                      LogoSize;

/** Offset 0x011E - BMP Logo Data Pointer
  BMP logo data pointer to a BMP format buffer.
**/
  uint32_t                      LogoPtr;

/** Offset 0x0122 - Graphics Configuration Data Pointer
  Graphics configuration data used for initialization.
**/
  uint32_t                      GraphicsConfigPtr;

/** Offset 0x0126 - GT PM Support
  Enable/Disable GT power management support.
  $EN_DIS
**/
  uint8_t                       PmSupport;

/** Offset 0x0127 - RC6(Render Standby)
  Enable/Disable render standby support.
  $EN_DIS
**/
  uint8_t                       EnableRenderStandby;

/** Offset 0x0128 - PAVP Enable
  Enable/Disable Protected Audio Visual Path (PAVP).
  $EN_DIS
**/
  uint8_t                       PavpEnable;

/** Offset 0x0129 - PAVP PR3
  Enable/Disable PAVP PR3
  $EN_DIS
**/
  uint8_t                       PavpPr3;

/** Offset 0x012A - CdClock Frequency selection
  0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4(Default): 624 MHz
  0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz
**/
  uint8_t                       CdClock;

/** Offset 0x012B - Enable/Disable PeiGraphicsPeimInit
  Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit
  $EN_DIS
**/
  uint8_t                       PeiGraphicsPeimInit;

/** Offset 0x012C - Enable/Disable Timer 8254 Clock Setting
  Enable/Disable Timer 8254 Clock
  $EN_DIS
**/
  uint8_t                       Timer8254ClkSetting;

/** Offset 0x012D
**/
  uint8_t                       ReservedFspsUpd[211];
} __attribute__((packed));

/** Fsp S Test Configuration
**/
struct FSP_S_TEST_CONFIG {

/** Offset 0x0200
**/
  uint32_t                      Signature;

/** Offset 0x0204
**/
  uint8_t                       ReservedFspsTestUpd[12];
} __attribute__((packed));

/** Fsp S Restricted Configuration
**/
struct FSP_S_RESTRICTED_CONFIG {

/** Offset 0x0210
**/
  uint32_t                      Signature;

/** Offset 0x0214
**/
  uint8_t                       ReservedFspsRestrictedUpd[12];
} __attribute__((packed));

#define FSPS_UPD_SIGNATURE               0x4450555F53505346        /* 'FSPS_UPD' */

struct FSPS_UPD {

/** Offset 0x0000
**/
  struct FSP_UPD_HEADER              FspUpdHeader;

/** Offset 0x0020
**/
  struct FSP_S_CONFIG                FspsConfig;

/** Offset 0x0200
**/
  struct FSP_S_TEST_CONFIG           FspsTestConfig;

/** Offset 0x0210
**/
  struct FSP_S_RESTRICTED_CONFIG     FspsRestrictedConfig;

/** Offset 0x0220
**/
  uint16_t                      UpdTerminator;
} __attribute__((packed));

#endif
